1. Field of the Invention
The present invention relates to a buffer circuit comprising a load, a follower transistor such as a source or emitter follower transistor, and a current source connected in series, the follower transistor providing an output potential signal from a source or emitter thereof, the output potential signal following a potential at the control input of the transistor.
2. Description of the Related Art
In optical communication, a high speed communication system exceeding 10 Gbps has been researched and developed in order to realize a large-capacity, long-distance communication, and improvement on wide band frequency characteristics, that is, to achieve a higher cut-off frequency is required for an optical transmission module of the communication system. Hence, a necessity has arisen to improve a frequency characteristic of an amplifying circuit in the optical transmission module. Further, power consumption of the amplifying circuit is a great part of that of an optical transmission module, and it can be expected that reduction in the power consumption of the amplifying circuit not only increases a transmission quality but also contributes to higher reliability of the entire optical transmission module.
FIG. 13 shows a prior art differential amplifier for use in an optical transmission module.
The differential amplifier has a symmetric configuration with respect to complementary inputs IN and IN*.
In a level shift circuit 10A, to obtain an input potential VI, the potential of an input signal IN provided to the gate of an enhancement FET (E-FET) 101 is lowered by a threshold voltage Vth between the gate and source thereof, and further lowered by a forward voltage Vf across a diode 102. For example, Vth=0.3 V and Vf=0.6 V.
In an input buffer circuit 11A, which is a source follower circuit, an E-FET 111 and a depletion FET (D-FET) 112 serving as a current source are connected in series between power supply lines VDD and VSS. The input potential VI is provided to the gate of the E-FET 111, and an output potential VO obtained by lowering the input potential VI by the threshold voltage Vth thereof is taken out from the source of the E-FET 111.
The output potential VO is provided to the gate of the E-FET 121, which is one input of a differential amplifier circuit 12.
A level shift circuit 10B and an input buffer circuit 11B are of the same configurations as those of the level shift circuit 10A and the input buffer circuit 11A, respectively. An input signal *IN is provided through the level shift circuit 10B and the buffer circuit 11B to the gate of an E-FET 122, which is the other input of the differential amplifier 12, as an output potential *VO.
In the input buffer circuit 11A, a current flows through the E-FET 111 and the D-FET 112 without regard to the level of the input potential VI. If design parameters of the D-FET 112 are determined so as to make the current to a small amount for a purpose of decreasing power consumption, then a time constant CR is increased due to increase in resistive component R, the response speed of the input buffer circuit 11A decreases, with the result that a frequency characteristic of the differential amplifier is deteriorated.
In order to solve this problem, a differential amplifier as shown in FIG. 14 was proposed.
In an input buffer circuit 11C, a DC bias potential which is obtained by dividing a voltage between power supply lines VDD and VSS by resistance R1 and R2 is applied to the gate of an E-FET 112A, while an AC component of the output *VO of an input buffer circuit 11D is provided thereto through a capacitor 113. Thereby, the current flowing through the E-FET 112A becomes variable. For example, when the output potentials VO rises and the output potential *VO falls, the gate potential of the E-FET 112A falls, the internal resistance of the E-FET 112A increases, and the output potential VO rises. Therefore it seems that the frequency characteristic would be improved without making the average consumed electric current of the E-FET 112A increase.
However, since the capacitance value of the capacitor 113 is made to a sufficiently larger than the gate capacitance value of the E-FET 112A, although the synthetic capacitance value of the capacitor 113 and the gate of the E-FET 112A becomes almost equal to the gate capacitance value of the E-FET112A, an input capacitance value of the differential amplifier circuit 12 viewed from the output of the input buffer circuit 11D becomes the sum of the gate capacitance value of the E-FET122 and the capacitance value of the capacitor 113, resulting in that a frequency characteristic of the input buffer circuit 11D is deteriorated. The same applies to the input buffer circuit 11C.
When two differential amplifiers of FIG. 14 are cascaded, since the buffer circuit 11C of the second stage differential amplifier also functions as an output buffer circuit of the first stage differential amplifier, this problem arises in an output buffer circuit.
Accordingly, it is an object of the present invention to provide a buffer circuit capable of improving a frequency characteristic without increasing a current consumption.
In one aspect of the present invention, there is provided a buffer circuit comprising a load, a follower transistor such as a source or emitter follower transistor, and a current source connected in series, the follower transistor providing an output potential signal from a source or emitter thereof, the output potential signal following a potential at the control input of the transistor. The current source has a control input receiving a DC bias, and has a current flowing therethrough depending on the control input potential thereof. A DC blocking circuit such as a capacitor is connected between the drain or emitter of the follower transistor and the control input of the current source.
With this configuration, when the control input potential of the follower transistor changes, the potential of the source or emitter of the transistor follows to this change with a time delay if the DC blocking circuit is not connected. However, with this connection, the current source operates so as to assist the following-up when this change arises without increasing an average current flowing through the current source. Further, in a state where a succeeding circuit such as an amplifier circuit is connected to the source or emitter of the transistor, since the capacitance viewed from the source or emitter of the transistor does not increase owing to connection of the DC blocking circuit, the response speed of the succeeding circuit is improved.
If a matching circuit such as an inductor is connected to the DC blocking circuit to constitute a band pass filter, the buffer circuit has an especially high gain at a resonance frequency thereof, therefore this configuration is effective in an analog circuit using a signal with a narrow frequency range near the resonance frequency.
Since an interconnection in the DC blocking circuit has a parasitic inductance at high frequencies, a band pass filter is constituted of the parasitic inductance and the DC blocking circuit, and the gain of the buffer circuit becomes especially high at the resonance frequency thereof. Therefore, when the buffer circuit is applied to a digital circuit requiring a wide band operation, high frequency noise has a chance to be included in the output waveform of the buffer circuit. In this case, a damping transistor is connected between the DC blocking circuit and the control input of the current source, and the potential of this control input is adjusted and then fixed so as to make a gain flat, by which high frequency noise can be prevented from being included in the output waveform.